* Use new MMUHEADmaster

Replace use of internal WIN_N registers by new MMU design

4 files changed, 29 insertions, 27 deletions

diff --git a/Makefile b/Makefile
index bd309f5..8f7312c 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@ TARGET=bootloader.hex
 CFLAGS=-mz80 -I. --Werror
 LDFLAGS=-mz80 --no-std-crt0 --code-loc 0x100 --data-loc 0x8000 -Wl-b_GSINIT=0x80
 
-ROM_CHIP=SST39SF020A
+ROM_CHIP=SST39SF040
 
 all : $(TARGET)
 
diff --git a/crt0.asm b/crt0.asm
index 567ab47..2a2c032 100644
--- a/crt0.asm
+++ b/crt0.asm
@@ -6,9 +6,9 @@
 	.area	_HEADER (ABS)
 	;; Reset vector
 	.org 	0x0000
-    ld      SP, #0x00
-    xor     A
-    ld      I, A
+    ld      sp, #0x00
+    xor     a
+    ld      i, a
     jp      init
     ;; ISR table
     .org    0x0010
@@ -26,18 +26,17 @@ _rx_isr_ptr:
     .dw     #_rx_isr
     ;; Init code
 init:
-    xor     A
-    ;; Enable extended memory
-    out     (WIN_0_CTRL), A
-    ld      A, #0b00100000
-    out     (WIN_1_CTRL), A
-    ld      A, #0b01000000
-    out     (WIN_2_CTRL), A
-    ld      A, #0b01100000
-    out     (WIN_3_CTRL), A
+    ;; Configure banking
+    ld      a, #0x81
+    out     (MMU_A), A
+    ld      a, #0x82
+    out     (MMU_B), A
 
-    ld      A, #SREG_EXT_MEM
-    out     (SREG_CTRL), A
+    ;; Disable PIO interrupts
+    ld      a, #0x07
+    out     (PORT_A_CTRL), a
+    ld      a, #0x07
+    out     (PORT_B_CTRL), a
 
     call	gsinit
 	call	_main
diff --git a/zbootloader.c b/zbootloader.c
index df168df..f1e931d 100644
--- a/zbootloader.c
+++ b/zbootloader.c
@@ -332,16 +332,19 @@ loop(void)
 int
 main(void)
 {
+	// Reset DMA
+	dma_ctrl = 0xC3;
+
     // Init CTC
     // 16 prescaler, timer mode
     ctc_channel_1 = (CTC_CLK_TRG_BIT | CTC_TIME_CONST_BIT | CTC_RST_BIT
                      | CTC_CTRL_OR_VECTOR_BIT);
-    ctc_channel_1 = (CPU_FREQ / 16 / 9600);
+    ctc_channel_1 = (CPU_FREQ / 16 / 9600); // 115200
 
     // 200Hz clock
     ctc_channel_3 = (CTC_INT_BIT | CTC_PRESCALER_BIT | CTC_CLK_TRG_BIT |
                      CTC_TIME_CONST_BIT | CTC_RST_BIT | CTC_CTRL_OR_VECTOR_BIT);
-    ctc_channel_3 = (CPU_FREQ / 256 / 36);
+    ctc_channel_3 = (CPU_FREQ / 256 / 144);
     ctc_channel_0 = ISR_OFFSET(ctc3_isr_ptr) | (3 << 1);
 
     // Init SIO
diff --git a/zeta.h b/zeta.h
index b5f08f9..02edbce 100644
--- a/zeta.h
+++ b/zeta.h
@@ -5,16 +5,8 @@
  * zeta hardware definitions
  */
 
-#define CPU_FREQ 1843200 // 1.8432 MHz
-
-#define EXT_CE_0 0x80
-#define EXT_CE_1 0x90
-#define EXT_CE_2 0xA0
-#define EXT_CE_3 0xB0
-#define EXT_CE_4 0xC0
-#define EXT_CE_5 0xD0
-#define EXT_CE_6 0xE0
-#define EXT_CE_7 0xF0
+/*  7372800UL 1.8432 MHz */
+#define CPU_FREQ 7372800UL
 
 // ********************************************************
 
@@ -131,6 +123,12 @@
 #define RTC_RAM_ADDRESS    0x70
 #define RTC_RAM_DATA       0x73
 
+// ********************************************************
+
+#define MMU_A    0x80
+#define MMU_B    0x81
+#define MMU_SREG 0x82
+
 //
 #ifndef ASSEMBLY
 
@@ -144,6 +142,8 @@ __sfr __at SIO_B_DATA sio_b_data;
 __sfr __at SIO_A_CTRL sio_a_ctrl;
 __sfr __at SIO_B_CTRL sio_b_ctrl;
 
+__sfr __at DMA_CTRL dma_ctrl;
+
 #define IM(__mode) __asm__("im " #__mode)
 #define EI __asm__("ei")
 #define DI __asm__("di")